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| 64-Position OTP Digital Potentiometer AD5273 FEATURES 64 Positions OTP (One-Time-Programmable)1 Set-and-Forget Resistance Setting--Low Cost Alternative Over EEMEM Unlimited Adjustments Prior to OTP Activation 1 k , 10 k , 50 k , 100 k End-to-End Terminal Resistance Compact SOT-23-8 Standard Package Ultralow Power: IDD = 5 A Max Fast Settling Time: tS = 5 s Typ in Power-Up I2C(R) Compatible Digital Interface Computer Software2 Replaces C in Factory Programming Applications Wide Temperature Range: -40 C to +105 C 6 V Programming Voltage Low Operating Voltage: 2.7 V to 5.5 V OTP Validation Check Function APPLICATIONS Systems Calibrations Electronics Level Settings Mechanical Potentiometers and Trimmers Replacement Automotive Electronics Adjustments Transducer Circuits Adjustments Programmable Filters up to 6 MHz BW3 GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SCL SDA I2C INTERFACE AND CONTROL LOGIC A W AD0 AD5273 WIPER REGISTER FUSE LINK B VDD GND In addition, for applications that program the AD5273 at the factory, Analog Devices offers device programming software2 running on Windows NT(R), 2000, and XP operating systems. This software application effectively replaces any external I2C controllers, which in turn enhances users' systems' time-to-market. The AD5273 is available in 1 k , 10 k , 50 k , and 100 k resistances, in a compact SOT-23 8-lead standard package, and operates from -40C to +105C. Along with its unique OTP feature, the AD5273 lends itself well to general digital potentiometer applications due to its effective resolution, array resistance options, small footprint, and low cost. An AD5273 evaluation kit and software are available. The kit includes the connector and cable that can be converted for factory programming applications. For applications that require dynamic adjustment of resistance settings with nonvolatile EEMEM, users should refer to the AD523x and AD525x families of nonvolatile memory digital potentiometers. The AD5273 is a 64-position, one-time-programmable (OTP) digital potentiometer4 that employs fuse link technology to achieve the permanent program setting. This device performs the same electronic adjustment function as most mechanical trimmers and variable resistors. It allows unlimited adjustments before permanently setting the resistance values. The AD5273 is programmed using a 2-wire, I2C compatible digital control. During the write mode, a fuse blow command is executed after the final value is determined, thereby freezing the wiper position at a given setting (analogous to placing epoxy on a mechanical trimmer). When this permanent setting is achieved, the value will not change, regardless of the supply variations or environmental stresses under normal operating conditions. To verify the success of permanent programming, Analog Devices patterned the OTP validation such that the fuse status can be discerned from two validation bits in the read mode. NOTES 1 One-Time-Programmable--unlimited adjustments before permanent setting. 2 ADI cannot guarantee the software to be 100% compatible in all systems due to the wide variations in computer configurations. 3 Applies to 1 k parts only. 4 The terms digital potentiometer, VR, and RDAC are used interchangeably. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD5273-SPECIFICATIONS ELECTRICAL CHARACTERISTICS 1 k, 10 k, 50 k, 100 k VERSIONS (VDD = 2.7 V to 5.5 V, VA < VDD, VB = 0 V, -40C < TA < +105C, unless otherwise noted.) Parameter DC CHARACTERISTICS RHEOSTAT MODE Resolution Resistor Differential NL2 (10 k, 50 k, 100 k) (1 k) Resistor Nonlinearity2 (10 k, 50 k, 100 k) (1 k) Nominal Resistance Tolerance3 (10 k, 50 k, 100 k) Nominal Resistance (1 k) Rheostat Mode Temperature Coefficient4 Wiper Resistance DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Differential Nonlinearity5 Integral Nonlinearity5 Voltage Divider4 Temperature Coefficient Full-Scale Error (10 k, 50 k, 100 k) (1 k) Zero-Scale Error (10 k, 50 k, 100 k) (1 k) RESISTOR TERMINALS Voltage Range6 Capacitance7 A, B Capacitance7 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Logic High (ADO) Input Logic Low (ADO) Input Logic Current Input Capacitance7 Output Logic Low (SDA) Three-State Leakage Current Output Capacitance7 POWER SUPPLIES Power Supply Range OTP Power Supply8 Supply Current OTP Supply Current9 Power Dissipation10 Power Supply Sensitivity Symbol Conditions Min Typ1 Max Unit N R-DNL R-INL RAB/RAB R RAB 6 RWB, VA = NC RWB, VA = NC RWB, VA = NC RWB, VA = NC TA = 25C -0.5 -1 -0.5 -5 -30 0.8 +0.05 +0.25 +0.10 +2 1.2 300 60 +0.5 +1 +0.5 +5 +30 1.6 100 Bits LSB LSB LSB LSB LSB % k ppm/C (RAB/RAB)/T Wiper = No Connect R RW IW = VDD/R, VDD = 3 V or 5 V DNL INL (VW/VW)/T VWFSE VWZSE Code = 0x20 Code = 0x3F Code = 0x00 -0.5 -0.5 -1 -1 -6 -6 0 0 GND +0.1 10 +0.5 +0.5 0 0 0 0 1 5 VDD LSB LSB ppm/C LSB LSB LSB LSB LSB LSB V pF pF nA VA, VB, VW CA, CB CW ICM VIH VIL VIH VIL IIL CIL VOL IOZ COZ VDD VDD_OTP IDD IDD_OTP PDISS PSRR PSRR f = 5 MHz, Measured to GND, Code = 0x20 f = 1 MHz, Measured to GND, Code = 0x20 VA = VB = VW 25 55 1 0.7 VDD -0.5 3.0 0 VDD + 0.5 0.3 VDD VDD 0.4 1 0.4 1 VIN = 0 V or 5 V 0.01 3 3 V V V V A pF V A pF V V A mA mW %/% %/% TA = 25C VIH = 5 V or VIL = 0 V TA = 25C, VDD = 6 V VIH = 5 V or VIL = 0 V, VDD = 5 V RAB = 1 k RAB = 10 k, 50 k, 100 k 2.7 6 100 -0.3 -0.05 0.1 0.2 5.5 6.5 5 0.03 +0.3 +0.05 -2- REV. C AD5273 Parameter Symbol Conditions R AB = 1 k, Code = 0x20 R AB = 10 k, Code = 0x20 R AB = 50 k, Code = 0x20 R AB = 100 k, Code = 0x20 VA = 1 V rms, R AB = 1 k, V B = 0 V, f = 1 kHz VA = 5 V 1 LSB Error Band, V B = 0, Measured at V W VA = 5 V 1 LSB Error Band, V B = 0, Measured at V W, V DD = 6 V VA = 5 V 1 LSB Error Band, VB = 0, Measured at VW RAB = 1 k, f = 1 kHz, Code = 0x20 RAB = 20 k, f = 1 kHz, Code = 0x20 k RAB = 50 k, f = 1 kHz, Code = 0x20 k RAB = 100 k, f = 1 kHz, Code = 0x20 k Min Typ 6000 600 110 60 0.05 5 400 5 3 13 20 28 400 1.3 0.6 1.3 0.6 0.6 0.1 Max Unit kHz kHz kHz kHz % s ms s nV/Hz Hz nV/Hz Hz nV/Hz Hz nV/Hz Hz kHz s s s s s s s s s s DYNAMIC CHARACTERISTICS7, 11, 12 Bandwidth -3 dB BW_1 k BW_10 k BW_50 k BW_100 k Total Harmonic Distortion THDW Adjustment Settling Time OTP Settling Time13 Power-Up Settling Time - Post Fuses Blown Resistor Noise Voltage tS1 tS_OTP tS2 eN_WB INTERFACE TIMING CHARACTERISTICS (applies to all parts7, 12, 14) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD; STA Hold Time (repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU; STA Setup Time for START Condition t5 tHD; DAT Data Hold Time t6 tSU; DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU; STO Setup Time for STOP Condition t10 50 0.9 0.3 0.3 0.6 NOTES 1 Typicals represent average readings at 25C, VDD = 5 V, and VSS = 0 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = No Connect. 4 RWB/T = RWA/T. Temperature coefficient is code dependent; see the Typical Performance Characteristics. R R 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Different from operating power supply, power supply for OTP is used one time only. 9 Different from operating current, supply current for OTP lasts approximately 400 ms for the one time it is needed. 10 PDISS is calculated from (IDD VDD). CMOS logic level inputs result in minimum power dissipation. 11 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 12 All dynamic characteristics use VDD = 5 V. 13 Different from settling time after fuses are blown. The OTP settling time occurs once only. 14 See Figure 1 for location of measured values. Specifications subject to change without notice. REV. C -3- AD5273 ABSOLUTE MAXIMUM RATINGS1 (TA = 25C, unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +6.5 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . GND, VDD Maximum Current IWB, IWA Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA IWB Continuous (RWB 1 k, A Open)2 . . . . . . . . . . . 4 mA IWA Continuous (RWA 1 k, B Open)2 . . . . . . . . . . . 4 mA Digital Input and Output Voltage to GND . . . . . . . . . . 0 V, VDD Operating Temperature Range . . . . . . . . . . . . -40C to +105C Maximum Junction Temperature (TJ MAX) . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Thermal Resistance3 JA, SOT-23 . . . . . . . . . . . . . . . . 230C/W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Package Power Dissipation = (TJ MAX - TA)/JA. ORDERING GUIDE Model AD5273BRJ1-R2 AD5273BRJ1-REEL7 AD5273BRJ10-R2 AD5273BRJ10-REEL7 AD5273BRJ50-R2 AD5273BRJ50-REEL7 AD5273BRJ100-R2 AD5273BRJ100-REEL7 AD5273EVAL Resistance RAB (k) 1 1 10 10 50 50 100 100 * Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 NA Package Description SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 Evaluation Board Number of Pieces on a REEL 250 3,000 250 3,000 250 3,000 250 3,000 * Branding DYA DYA DYB DYB DYC DYC DYD DYD NA *Users should order samples additionally as the evaluation kit comes with a socket but does not include the parts. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5273 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- REV. C AD5273 PIN CONFIGURATION W1 VDD 2 3 8A AD5273 7B TOP VIEW 6 AD0 GND (Not to Scale) SCL 4 5 SDA PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 Mnemonic W VDD GND SCL SDA AD0 B A Description Wiper Terminal W. GND VW VDD. Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be a minimum of 6 V and 100 mA driving capability. Common Ground. Serial Clock Input. Requires pull-up resistor. Serial Data Input/Output. Requires pull-up resistor. I2C Device Address Bit. Allows maximum of two AD5273s to be addressed. Resistor Terminal B. GND VB VDD. Resistor Terminal A. GND VA VDD. REV. C -5- AD5273-Typical Performance Characteristics 0.5 RAB = 10k TA = 25C RHEOSTAT MODE INL (LSB) 0.3 VDD = 3V 0.1 0.10 RAB = 10k TA = -40C TA = +85C 0.02 TA = +125C POTENTIOMETER MODE DNL (LSB) 0.06 -0.1 VDD = 5V -0.3 -0.02 TA = +25C -0.06 -0.5 0 8 16 24 32 40 CODE (Decimal) 48 56 64 -0.10 0 8 16 24 32 40 CODE (Decimal) 48 56 64 TPC 1. RINL vs. Code vs. Supply Voltages 0.25 RAB = 10k TA = 25C VDD = 5V 0.05 0.10 TPC 4. DNL vs. Code vs. Temperature POTENTIOMETER MODE INL (LSB) RAB = 10k TA = 25C 0.06 3V 0.02 RHEOSTAT MODE DNL (LSB) 0.15 -0.05 VDD = 3V -0.15 -0.02 5V -0.06 -0.25 0 8 16 24 32 40 CODE (Decimal) 48 56 64 -0.10 0 8 16 24 32 40 CODE (Decimal) 48 56 64 TPC 2. RDNL vs. Code vs. Supply Voltages 0.10 RAB = 10k POTENTIOMETER MODE DNL (LSB) POTENTIOMETER MODE INL (LSB) 0.06 TA = +85C 0.02 TA = +125C TPC 5. INL vs. Code vs. Supply Voltages 0.10 RAB = 10k TA = 25C 0.06 3V 0.02 -0.02 TA = +25C -0.06 -0.02 5V TA = -40C -0.06 -0.10 -0.10 0 8 16 24 32 40 CODE (Decimal) 48 56 64 0 8 16 24 32 40 CODE (Decimal) 48 56 64 TPC 3. INL vs. Code vs. Temperature TPC 6. DNL vs. Code vs. Supply Voltages -6- REV. C AD5273 0.025 POTENTIOMETER MODE LINEARITY (LSB) TA = 25C RAB = 10k CODE = 0x20 1.0 0.9 0.8 0.7 ZSE (LSB) 0.015 0.6 0.5 0.4 0.3 0.005 0.2 0.1 0 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 VDD = 5V VDD = 3V RAB = 10k 0.020 0.010 TPC 7. INL vs. Supply Voltage 0.4 TA = 25C RAB = 10k CODE = 0x20 SUPPLY CURRENT (A) 0.16 TPC 10. Zero-Scale Error VDD = 5.5V RAB = 10k RHEOSTAT MODE LINEARITY (LSB) 0.3 0.14 0.12 0.2 0.10 0.1 0.08 0 0.06 -0.1 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 0.04 -55 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 115 TPC 8. RINL vs. Supply Voltage 0 -0.1 -0.2 -0.3 FSE (LSB) -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 VDD = 3V SUPPLY CURRENT (mA) VDD = 5V RAB = 10k TPC 11. Supply Current vs. Temperature 10 TA = 25C RAB = 10k ALL DIGITAL PINS TIED TOGETHER 1 VDD = 5V 0.1 VDD = 2.7V 0.01 0.001 0.0001 0 1 2 3 4 INPUT LOGIC VOLTAGE (V) 5 6 TPC 9. Full-Scale Error TPC 12. Supply Current vs. Digital Input Voltage REV. C -7- AD5273 500 400 300 200 100 0 -100 -200 -300 100k 50k VDD = 5.5V TA = 25C 0 -6 MAGNITUDE (dB) 1k 10k -12 -18 -24 -30 -36 -42 -48 16 24 32 40 CODE (Decimal) 48 56 64 -54 100 0x00 0x3F 0x20 0x10 0x08 0x04 0x02 0x01 RHEOSTAT MODE TEMPCO (ppm/C) 0 8 1k 10k FREQUENCY (Hz) 100k 1M TPC 13. Rheostat Mode Tempco (RWB/RWB)/T vs. Code ( )/ 40 POTENTIOMETER MODE TEMPCO (ppm/C) VDD = 5.5V 30 20 10 0 -10 10k -20 -30 -40 1k 10k TPC 16. Gain vs. Frequency vs. Code, RAB = 10 k k 0 -6 MAGNITUDE (dB) -12 -18 -24 0x3F 0x20 0x10 0x08 0x04 0x02 -30 -36 -42 -48 0x01 10k 0 8 16 24 32 40 CODE (Decimal) 48 56 64 -54 100 0x00 1k 10k FREQUENCY (Hz) 100k 1M TPC 14. Potentiometer Mode Tempco (VW/VW)/T vs. Code ( )/ TPC 17. Gain vs. Frequency vs. Code, RAB = 50 k k 0x3F 0 -6 -12 MAGNITUDE (dB) -18 -24 -30 -36 -42 -48 -54 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0x02 0x20 0x10 MAGNITUDE (dB) 0x08 0x04 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 100 0x3F 0x20 0x10 0x08 0x04 0x02 0x01 0x01 0x00 0x00 1k 10k FREQUENCY (Hz) 100k 1M TPC 15. Gain vs. Frequency vs. Code, RAB = 1 k k TPC 18. Gain vs. Frequency vs. Code, RAB = 100 k k -8- REV. C AD5273 12 6 0 MAGNITUDE (dB) -6 -12 -18 -24 -30 -36 -42 -48 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 5V 5V 5s 50k 100k SCL = 5V/DIV 1k 10k VDD = 5.5V VA = 5.5V VB = GND DATA 0x00 0x3F fCLK = 400kHz VW = 5V/DIV TPC 19. -3 dB Bandwidth -80 POWER SUPPLY REJECTION RATIO (dB) TA = 25C CODE = 0x20 VA = 2.5V, VB = 0V -60 VDD = 5V DC 1.0V p-p AC VDD = 3V DC 0.6V p-p AC TPC 22. Large Settling Time fCLK = 100kHz DATA 0x20 0x1F VDD = 5.5V VA = 5.5V VB = GND -40 VW = 50mV/DIV -20 SCL = 5V/DIV 50mV 0 100 1k 10k FREQUENCY (Hz) 100k 1M 5V 200ns TPC 20. PSRR vs. Frequency TPC 23. Midscale Glitch Energy VDD = 5.5V VA = 5.5V VB = GND fCLK = 100kHz OTP PROGRAMMED AT MS VDD = 5.5V VA = 5.5V RAB = 10k VW = 10mV/DIV VW = 1V/DIV w VDD = 5V/DIV SCL = 5V/DIV 10mV 5V 500ns 1V 5V 5s TPC 21. Digital Feedthrough TPC 24. Power-Up Settling Time after Fuses Blown REV. C -9- AD5273 10 VA = VB = OPEN TA = 25C THEORETICAL IWB_MAX (mA) RAB = 1k 1.0 RAB = 10k RAB = 50k 0.1 RAB = 100k 0.01 0 8 16 24 32 40 CODE (Decimal) 48 56 64 TPC 25. IWB_MAX vs. Code t8 t9 t6 SCL t2 t3 t8 SDA t4 t9 t5 t7 t10 t1 P S P Figure 1. Interface Timing Diagram Table I. SDA Write Mode Bit Format S 0 1 0 1 1 0 AD0 0 A T X X X X X X X A X X D5 D4 D3 D2 D1 D0 A P SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE Table II. SDA Read Mode Bit Format S 0 1 0 1 1 0 AD0 1 A E1 E0 D5 D4 D3 D2 D1 D0 A P SLAVE ADDRESS BYTE DATA BYTE SDA BIT DEFINITIONS AND DESCRIPTIONS S = Start Condition. P = Stop Condition. A = Acknowledge. X = Don't Care. T = OTP Programming Bit. Logic 1 programs wiper position permanently. D5, D4, D3, D2, D1, D0 = Data Bits. E1, E0 = OTP Validation Bits. -10- 0, 0 = Ready to Program. 0, 1 = Test Fuse Not Blown Successfully. (For factory setup checking purpose only. Users should not see these combinations.) 1, 0 = Fatal Error. Do not retry. Discard the unit. 1, 1 = Programmed Successfully. No further adjustments possible. AD0 = I2C Device Address Bit. Allows maximum of two AD5273s to be addressed. REV. C AD5273 Figure 2. Detailed Functional Block Diagram THEORY OF OPERATION The AD5273 is a one-time-programmable (OTP), set-andforget, 6-bit digital potentiometer. The AD5273 allows unlimited 6-bit adjustments prior to the OTP. OTP technology is a proven cost-effective alternative over EEMEM in one-time memory programming applications. The AD5273 employs fuse link technology to achieve the memory retention of the resistance setting function. It comprises six data fuses, which control the address decoder for programming the RDAC, one user mode test fuse for checking setup error, and one programming lock fuse for disabling any further programming once the data fuses are programmed correctly. ONE-TIME PROGRAMMING (OTP) Prior to OTP activation, the AD5273 presets to midscale during power on. After the wiper is set at the desired position, the resistance can be permanently set by programming the T bit to high along with the proper coding (Table I). Note that the fuse link technology requires 6 V to blow the internal fuses to achieve a given setting. The user is allowed only one attempt at blowing the fuses. Once programming is completed, the power supply voltage must be reduced to the normal operating range of 2.7 V to 5.5 V. The device control circuit has two validation bits, E1 and E0, that can be read back in the read mode for checking the programming status as shown in Table III. Users should always read back the validation bits to ensure that the fuses are properly blown. Table III. Validation Status When the OTP T bit is set, the internal clock is enabled. The program will attempt to blow a test fuse. The operation stops if this fuse is not blown properly. The validation Bits E1 and E0 show 01. This status is intended for factory setup checking purpose only so users should not see such status. If the test fuse is blown successfully, the data fuses will be programmed next. The six data fuses will be programmed in six clock cycles. The output of the fuses is compared with the code stored in the DAC register. If they do not match, E1 and E0 of 10 are issued as a fatal error and the operation stops. Users should never try blowing the fuses for more than one attempt because the fuse structure may have changed that prohibits further programming. As a result, users must discard the unit. This error status can occur if the OTP supply voltage droops below 6 V, the OTP supply current is limited, or both the voltage and current ramp times are slow. If the output and stored code match, the programming lock fuse will be blown so that no further programming is possible. In the meantime, E1 and E0 will issue 11 indicating the lock fuse is blown successfully. All the fuse latches are enabled at power-on and therefore the output corresponds to the stored setting from this point on. Figure 2 shows a detailed functional block diagram. DETERMINING THE VARIABLE RESISTANCE AND VOLTAGE Rheostat Mode Operation E1 0 0 1 1 E0 0 1 0 1 Status Ready for Programming Test Fuse Not Blown Successfully. (For factory setup checking purpose only. Users should not see these combinations.) Fatal Error. Some fuses are not blown. Do not retry. Discard the unit. Successful. No further programming is possible. If only the W-to-B or W-to-A terminals are used as variable resistors, the unused terminal can be opened or shorted with W. This operation is called rheostat mode (Figure 3). Figure 3. Rheostat Mode Configuration REV. C -11- AD5273 The nominal resistance (RAB) of the RDAC has 64 contact points accessed by the wiper terminal, plus the B terminal contact if RWB is considered. The 6-bit data in the RDAC latch is decoded to select one of the 64 settings. Assuming that a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Such connection yields a minimum of 60 resistance between terminals W and B because of the 60 wiper contact resistance. The second connection is the first tap point, which corresponds to 219 (RWB = (1) RAB/63 + RW) for data 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10060 ((63) RAB/63 + RW). Figure 4 shows a simplified diagram of the equivalent RDAC circuit. The general equation determining RWB is RWB ( D ) = where: D is the decimal equivalent of the 6-bit binary code. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. Table IV. RWB vs. Codes; RAB = 10 k and the A Terminal Is Opened Figure 4. AD5273 Equivalent RDAC Circuit Potentiometer Mode Operation The typical distribution of the resistance tolerance from device to device is process lot dependent, and it is possible to have 30% tolerance. D x RAB + RW 63 (1) If all three terminals are used, the operation is called the potentiometer mode. The most common configuration is the voltage divider operation (Figure 5). D (Dec) 63 32 1 0 RWB () 10060 5139 219 60 Output State Full-Scale (RAB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance) Since a finite wiper resistance of 60 is present in the zero-scale condition, care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a complementary resistance RWA. When these terminals are used, the B terminal can be opened or shorted to W. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RWA (D) = 63 - D x RAB + RW 63 (2) Figure 5. Potentiometer Mode Configuration Ignoring the effect of the wiper resistance, the transfer function is simply VW (D) = D VA 63 (3) A more accurate calculation, which includes the wiper resistance effect, yields D R + RW 63 AB VW ( D ) = V RAB + 2RW A (4) Table V. RWA vs. Codes; RAB =10 k and B Terminal Is Opened D (Dec) 63 32 1 0 RWA () 60 4980 9901 10060 Output State Full-Scale Midscale 1 LSB Zero-Scale Unlike in rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratio-metric function of D/63 with a relatively small error contributed by the RW terms, and therefore the tolerance effect is almost cancelled. Although the thin film step resistor RS and CMOS switches resistance RW have very different temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/C, except at low value codes where RW dominates. Potentiometer mode operations include others such as op amp input, feedback resistor networks, and other voltage scaling applications. A, W, and B terminals can in fact be input or output terminals provided that |VAB|, |VWA|, and |VWB| do not exceed VDD to GND. -12- REV. C AD5273 ESD PROTECTION Digital inputs SDA and SCL are protected with a series input resistor and parallel Zener ESD structures (Figure 6). Figure 6. ESD Protection of Digital Pins TERMINAL VOLTAGE OPERATING RANGE Figure 8. Power Supply Requirement There are also ESD protection diodes between VDD and the RDAC terminals. The VDD of AD5273 therefore defines their voltage boundary conditions, see Figure 7. Supply signals present on terminals A, B, and W that exceed VDD will be clamped by the internal forward-biased diodes and should be avoided. An alternate approach in 3.5 V to 5.5 V systems adds a signal diode between the system supply and the OTP supply for isolation, as shown in Figure 9. Figure 9. Isolating the 6 V OTP Supply from the 3.5 V to 5.5 V Normal Operating Supply. The 6 V supply must be removed once OTP is complete. Figure 7. Maximum Terminal Voltages Set by VDD POWER-UP/POWER-DOWN SEQUENCES Similarly, because of the ESD protection diodes, it is important to power VDD first before applying any voltages to terminals A, B, and W. Otherwise, the diode will be forward-biased such that VDD will be powered unintentionally and may affect the rest of the users' circuits. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD. Similarly, VDD should be powered down last. POWER SUPPLY CONSIDERATIONS To minimize the package pin count, both the one-time programming and normal operating voltage supplies are applied to the same VDD terminal of the AD5273. The AD5273 employs fuse link technology that requires 6 V to blow the internal fuses to achieve a given setting. The user is allowed only one attempt at blowing the fuses. Once programming is complete, power supply voltage must be reduced to the normal operating range of 2.7 V to 5.5 V. Such dual voltage requires isolation between supplies. The fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 6 V and must be able to provide 100 mA transient current for 400 ms in order for successful one-time programming. Once programming is complete, the 6 V supply must be removed to allow normal operation of 2.7 V to 5.5 V at regular microamp current levels. Figure 8 shows the simplest implementation using a jumper. This approach saves one voltage supply but draws additional current and requires manual configuration. Figure 10. Isolating the 6 V OTP Supply from the 2.7 V Normal Operating Supply. The 6 V supply must be removed once OTP is complete. For users who operate their systems at 2.7 V, it is recommended to use the bi-directional low threshold P-Ch MOSFETs for the supplies isolation. Figure 10 assumes that the 2.7 V system voltage is first applied. The gates of P1 are P2 are pulled to ground, which turns on P1 and subsequently P2. As a result, VDD of AD5273 approaches 2.7 V. When the AD5273 setting is found, the factory tester applies the 6 V to VDD and also to the gates of P1 and P2 to turn them off. While the OTP command is executing at this time to program AD5273, the 2.7 V source is therefore protected. Once the OTP is complete, the tester withdraws the 6 V, and AD5273 setting is permanently fixed. The AD5273 achieves the OTP function through blowing internal fuses. Users should always apply the 6 V one-time program voltage requirement at the first program command. Noncompliance of such a requirement may lead to the change of the fuse structures, rendering inoperable programming. Poor PCB layout introduces parasitic that may also affect the fuse programming. Therefore, it is recommended to add a 1 nF ceramic capacitor in parallel with 1 F tantalum capacitor as close as possible to the VDD pin. These capacitors provide the extra transient currents that make the PCB layout variations less sensitive to the OTP programming error. REV. C -13- AD5273 Figure 11. Computer Software CONTROLLING THE AD5273 There are two ways of controlling the AD5273. Users can either program the device with computer software or with external I2C controllers. Software Programming layout into which pogo pins can be inserted for factory programming. To prevent damaging the PC parallel port, 100 resistors should also be put in series to the SCL and SDA pins. Pull-up resistors on SCL and SDA are also required. 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 Due to the advantage of the one-time programmable feature, most systems using the AD5273 will program the devices in the factory before shipping them to the end users. As a result, ADI offers device programming software that can be implemented in the factory on computers running Windows NT, 2000, and XP platforms. The software, which can be downloaded from the AD5273 product folder at www.analog.com is an executable file that does not require any programming languages or user programming skills. Figure 11 shows the software interface. Write VDD R4 10k SCL R2 100 READ 100 R1 WRITE SDA R5 10k The AD5273 starts at midscale after power-up prior to any OTP programming. To increment or decrement the resistance, the user may simply move the scrollbar on the left. Once the desired setting is found, the user can press the Program Permanent button to lock the setting permanently. To write any specific values, the user should use the bit pattern control in the upper screen and press the Run button. The format of writing data to the device is shown in Table I. Once the desired setting is found, the user can turn the T bit to 1 and press the Run button to program the setting permanently. Read R3 100 To read the validation bits and data out from the device, the user can simply press the Read button. The user can also set the bit pattern in the upper screen and press the Run button. The format of reading data out from the device is shown in Table II. In both read and write operations, the program generates the I2C digital signals through the parallel port LPT1 Pins 2, 3, 15, and 25 for SDA_write, SCL, SDA_read, and DGND, respectively, to control the device (see Figure 12). To apply the device programming software in the factory, users may lay out the AD5273 SCL and SDA pads on the PCB such that the programming signals can be communicated to and from the parallel port. Figure 13 shows a recommended AD5273 PCB Figure 12. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND. W VDD DGND SCL A B AD0 SDA Figure 13. Recommended AD5273 PCB Layout. The SCL and SDA pads allow pogo pins to be inserted so that signals can communicate through the parallel port for programming. Refer to Figure 8. -14- REV. C AD5273 I2C Controller Programming Write Bit Pattern Illustrations 0 SCL SDA 0 1 0 1 1 0 AD0 R/W ACK. BY AD5273 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE 0 X X X X X X X X ACK. BY AD5273 FRAME 1 DATA BYTE X D5 D4 D3 D2 D1 D0 ACK. BY AD5273 STOP BY MASTER 8 0 8 0 8 Figure 14a. Writing to the RDAC Register 0 SCL SDA 0 1 0 1 1 0 AD0 R/W ACK. BY AD5273 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE 1 X X X X X X X X ACK. BY AD5273 FRAME 1 DATA BYTE X D5 D4 D3 D2 D1 D0 ACK. BY AD5273 STOP BY MASTER 8 0 8 0 8 Figure 14b. Activating One-Time Programming Read Bit Pattern Illustration 0 SCL SDA 0 1 0 1 1 0 AD0 R/W ACK. BY AD5273 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 DATA BYTE FROM SELECTED RDAC REGISTER E1 E0 D5 D4 D3 D2 D1 D0 NO ACK. BY MASTER STOP BY MASTER 8 0 8 Figure 15. Reading Data from the RDAC Register For users who do not use the software solution, the AD5273 can be controlled via an I2C compatible serial bus and is connected to this bus as a slave device. Referring to Figures 14a, 14b, and 15, the 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is when SDA goes from high to low while SCL is high (Figure 14a). The following byte is the slave address byte, which consists of the six MSBs as slave address defined as 010110. The next bit is AD0; it is an I2C device address bit. Depending on the states of their AD0 bits, two AD5273s can be addressed on the same bus (see Figure 16). The last LSB is the R/W bit, which determines whether data will be read from R/W or written to the slave device. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. A write operation contains one more instruction byte than the read operation. The instruction byte in the write mode follows the slave address byte. The MSB of the instruction byte labeled T is the one-time programming bit. After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 14a). 3. In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (slight difference with the write mode, there are eight data bits followed by a no acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL as shown in Figure 11. 4. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In the write mode, the master will pull the SDA line high during the 10th clock pulse to establish a stop condition (see Figures 14a and 14b). In the read mode, the master will issue a no acknowledge for the ninth clock pulse, i.e., the SDA line remains high. The master will then bring the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (see Figure 15). A repeated write function gives the user flexibility to update the RDAC output a number of times, except after permanent programming, after addressing and instructing the part only once. During the write cycle, each data byte will update the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output will update after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the write mode has to be started again with a new slave address, instruction, and data bytes. Similarly, a repeated read function of the RDAC is also allowed. REV. C -15- AD5273 CONTROLLING TWO DEVICES ON ONE BUS Programmable Current Source Figure 16 shows two AD5273 devices on the same serial bus. Each has a different slave address since the state of each AD0 pin is different. This allows each device to operate independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface. 5V Rp Rp SDA MASTER SCL A programmable current source can be implemented with the circuit shown in Figure 19. The load current is simply the voltage across terminals B-to-W of the AD5273 divided by RS. Notice that at zero-scale, the A terminal of the AD5273 will be at -2.048 V, which makes the wiper voltage clamped at ground potential. Dependent on the load, Equation 5 is therefore valid only at certain codes. For example, when the compliance voltage VL equals half of the VREF, the current can be programmed from midscale to full-scale of the AD5273. 5V 2 3 U1 VS 6 0 TO (2.048 + VL) AD5273 SDA SCL AD0 5V AD5273 SDA SCL AD0 OUTPUT SLEEP Figure 16. Two AD5273 Devices on One Bus APPLICATIONS Programmable Voltage Reference (DAC) REF191 GND 4 AD5273 C1 1F A U3 B W RS 102 U2 +5V IL It is common to buffer the output of the digital potentiometer as a DAC unless the load is much larger than RWB. The buffer serves the purpose of impedance conversion as well as delivering high current, which may be needed. 5V 1 U1 VOUT 3 V+ VL RL 100 OP1177 -2.048 + VL V- -5V AD5273 AW B U3 Figure 19. Programmable Current Source 5V VIN U2 AD8601 VO IL = GND 2 ADR03 (VREF x D ) / 64 32 D 63 RS (5) Gain Control Compensation Figure 17. Programmable Voltage Reference (DAC) Programmable Voltage Source with Boosted Output As shown in Figure 20, the digital potentiometers are commonly used in gain controls or sensor transimpedance amplifier signal conditioning applications. C2 4.7pF 4.7p B R2 A R1 47k 100k W U1 C1 VI VO For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 18). VIN U3 2N7002 VOUT CC SIGNAL LD RBIAS IL AD5273 U1 A +V W U2 AD8601 -V B Figure 18. Programmable Booster Voltage Source Figure 20. Typical Noninverting Gain Amplifier In this circuit, the inverting input of the op amp forces the VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-Ch FET N1. N1 power handling must be adequate to dissipate (VIN - VOUT) IL power. This circuit can source a maximum of 100 mA with a 5 V supply. For precision applications, a voltage reference, such as the ADR421, ADR03, or ADR370, can be applied at the A terminal of the digital potentiometer. In both applications, one of the digital potentiometer terminals is connected to the op amp inverting node with finite terminal capacitance C1. It introduces a zero for the 1 o term with 20 dB/dec, whereas a typical op amp GBP has -20 dB/dec characteristics. A large R2 and finite C1 can cause this zero's frequency to fall well below the crossover frequency. Therefore, the rate of closure becomes 40 dB/dec and the system has 0 phase margin at the crossover frequency. The output may ring, or in the worst case, oscillate when the input is a step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. To reduce the effect of C1, users should also configure B or A rather than W terminal at the inverting node. -16- REV. C AD5273 Depending on the op amp GBP, reducing the feedback resistor may extend the zero's frequency far enough to overcome the problem. A better approach is to include a compensation capacitor C2 to cancel the effect caused by C1. Optimum compensation occurs when R1 C1 = R2 C2. This is not an option because of the variation of R2. As a result, one may use the relationship above and scale C2 as if R2 were at its maximum value. Doing so may overcompensate by slowing down the settling time when R2 is set at low values. As a result, C2 should be found empirically for a given application. In general, C2 in the range of a few picofarads to no more than a few tenths of a picofarad is adequate for the compensation. There is also a W terminal capacitance connected to the output (not shown); its effect on stability is less significant so that the compensation may not be necessary unless the op amp is driving a large capacitive load. Programmable Low-Pass Filter VDD1 = 2.5V Rp Rp Rp Rp VDD2 = 5V G SDA1 SCL1 S M1 D S M2 2.5V CONTROLLER 2.7V-5.5V G D SDA2 SCL2 AD5273 Figure 22. Level Shift for Different Voltage Operation Resistance Scaling In A/D conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. To minimize various system redesigns, users can use two 1 k AD5273s to construct a generic second-order Sallen Key low-pass filter. Since the AD5273 is a single-supply device, the input must be dc offset when an ac signal is applied to avoid clipping at ground. This is illustrated in Figure 21. The design equations are VO = VI O O 2 2 S+ S + O Q 1 R1R2C1C 2 2C 2 The AD5273 offers 1 k, 10 k, 50 k, and 100 k nominal resistances. For users who need to optimize the resolution with an arbitrary full-range resistance, the following techniques can be the solutions. Applicable only to the voltage divider mode, by paralleling a discrete resistor as shown in Figure 23, a proportionately lower voltage appears at terminal A-B. This translates into a finer degree of precision because the step size at terminal W will be smaller. The voltage can be found as VW ( D ) = (RAB || R2) x D x V DD R3 + RAB || R2 63 VDD R3 (9) (6) o = (7) R2 A R1 B W Q= 1 1 + R1C1 R2C 2 (8) Figure 23. Lowering the Nominal Resistance Users can first select some convenient values for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, R1 and R2 can be adjusted to the same setting to achieve the desirable bandwidth. C1 C B W C2 C +2.5V V+ AD8601 V- ADJUSTED TO SAME SETTINGS U1 -2.5V VO VI A R1 B A R2 Figure 23 shows that the digital potentiometer changes steps linearly. On the other hand, log taper adjustment is usually preferred in applications like volume control. Figure 24 shows another way of resistance scaling. In this circuit, the smaller the R2 with respect to RAB, the more it behaves like the pseudo log taper characteristic. The wiper voltage is simply VW ( D ) = W RWA ( D ) + RWB ( D ) || R 2 VI A R1 B W R2 VO (RWB (D)|| R2) x VI (10) Figure 21. Sallen Key Low-Pass Filter Level Shift for Different Voltages Operation When users need to interface a 2.5 V controller with the AD5273, a proper voltage level shift must be employed so that the digital potentiometer can be read from or written to the controller; Figure 22 shows one of the implementations. M1 and M2 should be low threshold N-Ch power MOSFETs, such as the FDV301N. Figure 24. Resistor Scaling with Log Adjustment Characteristics REV. C -17- AD5273 Resolution Enhancement A CA 25pF W 1k CW 55pF B CB 25pF Borrowing from ADI's patented RDAC segmentation technique, users can configure three AD5273s to double the resolution (see Figure 25). First, U3 must be paralleled with a discrete resistor RP that is chosen to be equal to a step resistance (RP = RAB/64). Adjusting U1 and U2 together forms the coarse 6-bit adjustment and adjusting U3 alone forms the finer 6-bit adjustment. As a result, the effective resolution becomes 12-bit. A1 U1 B1 A2 U2 B2 COARSE ADJUSTMENT FINE ADJUSTMENT W1 A3 RP U3 B3 W2 W3 Figure 26. Circuit Simulation Model for RDAC = 1 k k Macro Model Net List for RDAC .PARAM D = 63, RDAC = 1E3 * .SUBCKT DPOT (A,W,B) * CA RWA CW RWB CB * .ENDS DPOT A A W W B 0 W 0 B 0 25E-12 {(1-D/63)*RDAC+60} 55E-12 {D/63*RDAC+60} 25E-12 Figure 25. Double the Resolution in Rheostat Mode Operation RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the digital potentiometers. Configured as a potentiometer divider, the -3 dB bandwidth of the AD5273 (1 k resistor) measures 6 MHz at half scale. TPCs 15 to 18 provide the large signal BODE plot characteristics of the four available resistor versions 1 k, 10 k, 50 k, and 100 k. Figure 26 shows a parasitic simulation model. The code following Figure 26 provides a macro model net list for the 1 k device. -18- REV. C AD5273 EVALUATION BOARD JP5 JP3 VDD V+ C7 10F VCC VDD C4 0.1F U4 5 1 TEMP TRIM 2 3 GND 4 VIN VOUT ADR03 C6 0.1F CP3 -IN1 -IN1 CP4 CP2 JP1 A W VIN JP8 JP7 CP1 2 3 4 CP5 8 1 U3A CP6 V- C5 0.1F VREF OUT1 VDD VDD C1 10F R2 10k C2 0.1F U1 1 A 2W V B 3 DD GND AD0 4 SCL SDA 8 7 6 5 U2 1 A 2W B 3 VDD GND AD0 4 SCL SDA 8 7 6 5 JP2 B +IN1 CP7 OUT1 J1 8 7 6 5 4 3 2 1 R1 10k C3 0.1F AGND JP4 C8 0.1F JP6 -IN2 6 7 5 U3B OUT2 SCL SDA AD5170 AD5171/AD5273 C9 10F VEE +IN2 Figure 27. Evaluation Board Schematic CP2 VREF VREF A B W A VO U2 B W JP2 VDD JP3 4 U3A V+ 1 V- 11 JP4 OUT1 JP1 JP7 2 3 AD822 Figure 28. One of the Possible Configurations: Programmable Voltage Reference Figure 29. Evaluation Board REV. C -19- AD5273 OUTLINE DIMENSIONS 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters 2.90 BSC 8 7 6 5 1.60 BSC 1 2 3 4 2.80 BSC PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC 1.45 MAX 0.38 0.22 0.22 0.08 8 4 0 0.15 MAX SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178BA -20- REV. C AD5273 Revision History Location 11/03--Data Sheet changed from REV. B to REV. C. Page Changes to SDA BIT DEFINITIONS AND DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to ONE-TIME PROGRAMMING (OTP) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to POWER SUPPLY CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to Figures 8, 9, and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10/03--Data Sheet changed from REV. A to REV. B Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPCs 7, 8, 13, and 14 captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Deleted TPC 20; renumbered successive TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Change to TPC 21 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Change to the SDA BIT DEFINITIONS AND DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Replaced THEORY OF OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Replaced DETERMINING THE VARIABLE RESISTANCE AND VOLTAGE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Replaced ESD PROTECTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Replaced TERMINAL VOLTAGE OPERATING RANGE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Replaced POWER-UP SEQUENCE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Replaced POWER SUPPLY CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to APPLICATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Change to Equation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Deleted Digital Potentiometer Family Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6/03--Data Sheet changed from REV. 0 to REV. A. Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to POWER SUPPLY CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REV. C -21- -22- -23- -24- C03224-0-11/03(C) |
Price & Availability of AD5273BRJ1-R2
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